VSync 924 Specifikace stáhnout pdf (Strana 47)

Matrox Solios eCL/XCL acquisition section 47

Performance

The video timing parameters supported by the board are as follows:

The maximum pixel clock frequency is dependent on the length of the cable used.

Refer to the Technical features of Matrox Solios eCL/XCL section.

Acquisition

A Base-type acquisition path supports a maximum of 24 bits of video data when

acquiring from Camera Link-compliant video sources or up to 32 bits when

acquiring from non-standard time-multiplexed video sources. Similarly, a

Medium-type acquisition path can grab up to 48 bits of video data when acquiring

from Camera Link-compliant sources or up to 64 bits when acquiring from non-

standard time-multiplexed sources. Finally, a Full-type acquisition path supports

up to 64 bits of video data when acquiring from Camera Link-compliant video

sources and up to 80 bits when acquiring from non-standard video sources.

Maximum

Number of pixels / line (including sync and blanking) 64 K

Number of lines / frame (including sync and blanking) 64 K

Pixel clock

eCL/XCL-B 85 Mhz

eCL/XCL dual-Base/single-Medium without fast Camera Link option 66 Mhz

eCL/XCL dual-Base/single-Medium with fast Camera Link option 85 Mhz

eCL/XCL-F 85 Mhz

Bandwidth

eCL/XCL-B 255 Mbytes/sec

eCL/XCL dual-Base/single-Medium without fast Camera Link option 396 Mbytes/sec

eCL/XCL dual-Base/single-Medium with fast Camera Link option 510 Mbytes/sec

eCL/XCL-F 680 Mbytes/sec

1 2 ... 42 43 44 45 46 47 48 49 50 51 52 ... 159 160

Žádné komentáře

VSync 924 Specifikace Strana 47