VSync 924 Specifikace stáhnout pdf (Strana 131)

Connectors on Matrox Solios eCL/XCL dual-Base/single-Medium and eCL/XCL-F boards 131

JTAG connector

If Matrox Solios eCL/XCL has the optional Processing FPGA, the board features

a 10-pin male JTAG connector for debugging and probing internal signals of the

FPGA. The pin assignment, as used in JTAG mode, is as follows:

You can connect to the JTAG connector with a standard Altera ByteBlaster II cable

that can be purchased from the Altera Corporation. To begin debugging, you must

first enable the connector by installing a jumper on the adjacent 2-pin connector

(J2).

For further information on debugging with the JTAG connector, refer to the

Quartus II documentation from the Altera Corporation. For other debugging

information, refer to the Matrox Solios FPGA Developer’s Toolkit (FDK) manual.

Pin Hardware signal name Description

1 TCK Clock signal.

2 GND Signal ground.

3 TDO Data from device.

4 VCC(TRGT) Target power supply.

5 TMS JTAG state machine control.

6 No connect No connect.

7 No connect No connect.

8 No connect No connect.

9 TDI Data to device.

10 GND Signal ground.

1 2 ... 126 127 128 129 130 131 132 133 134 135 136 ... 159 160

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VSync 924 Specifikace Strana 131